It is discovered that in semiconductor devices (for example, those formed on a silicon substrate), electrons have high mobility in a silicon substrate the crystal face orientation of which is (100), and holes have high mobility in a silicon substrate the crystal face orientation of which is (110). At the same time, CMOS techniques, the leading technology for very-large-scale integration, involve forming PMOS transistors and NMOS transistors on the same substrate. Therefore, in order to improve device performances and reduce circuit response time, it is desirable to integrate a (100) silicon surface and a (110) silicon surface in a single substrate, and form NMOS transistors on the (100) silicon substrate and form PMOS transistors on the (110) silicon substrate, i.e., to form a hybrid channel semiconductor device.
FIGS. 1-4 illustrate a conventional method for forming a hybrid channel semiconductor device.
As shown in FIG. 1, a first semiconductor layer 10 is provided, and the first semiconductor layer 10 is (100) monocrystalline silicon. A second semiconductor layer 11 is formed on the first semiconductor layer 10 by Direct Silicon Bonding (DSB), and the second semiconductor layer 11 is (110) monocrystalline silicon. The first semiconductor layer 10 consists of area I, area II and area III. P-wells (not shown) are formed in area I and area III, N-wells (not shown) are formed in area II, and Shallow Trench Isolation (STI) 12 structures are formed at the interface between the areas.
As shown in FIG. 2, a mask pattern 13 is formed on the second semiconductor layer 11 in area II. The mask pattern 13 may be a photoresist pattern or a hardmask pattern. By using the mask pattern 13 as a mask, ion implantation is performed on the second semiconductor layer 11, such that the second semiconductor layer 11 in area I and area III is amorphized to form an amorphous silicon layer 11a. 
As shown in FIG. 3, by Solid Phase Epitaxy (SPE), the amorphous silicon layer in area I and area III is converted to a monocrystalline silicon layer 11b, and the crystal face orientation of the monocrystalline silicon layer 11b is the same as that of the first semiconductor layer 10, i.e., (100). Thus, the crystal face orientation of the monocrystalline silicon layer 11b in area I and area III on the surface of the first semiconductor layer 10 is (100), and the crystal face orientation of the second semiconductor layer 11 is (110).
As shown in FIG. 4, then, by a conventional CMOS process in the prior art, NMOS transistors 14 and 16 are formed in both area I and area III, and a PMOS transistor 15 is formed in area II.
For more information on the method described above, please refer to “Direct Silicon Bonded (DSB) Substrate Solid Phase Epitaxy (SPE) Integration Scheme Study for High Performance Bulk CMOS” by Haizhou Yin et al. published on “Electron Devices Meeting, 2006. IEDM '06. International”.
However, in the method above, the amorphization of the second semiconductor layer 11 by ion implantation as shown in FIG. 2 may introduce defects in the amorphous silicon layer 11a in area I and area III; and the defects will remain in the recrystallized monocrystalline silicon layer 11b shown in FIG. 3. If the defects are located in the channel region of the NMOS transistor 14 or 16 shown in FIG. 4, the performances of the NMOS transistor 14 or 16 will be degraded.